[^:]*: Assembler messages:
[^:]*:3: Error: bad type in SIMD instruction -- `vidup.s16 q0,r0,#1'
[^:]*:4: Error: bad type in SIMD instruction -- `vidup.u64 q0,r0,#1'
[^:]*:5: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#3'
[^:]*:6: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#0'
[^:]*:7: Error: bad type in SIMD instruction -- `viwdup.s16 q0,r0,r1,#1'
[^:]*:8: Error: bad type in SIMD instruction -- `viwdup.u64 q0,r0,r1,#1'
[^:]*:9: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#3'
[^:]*:10: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#0'
[^:]*:11: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:12: Error: r15 not allowed here -- `viwdup.u32 q0,r0,pc,#1'
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
[^:]*:30: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
[^:]*:32: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vidupt.u32 q0,r0,#1'
[^:]*:35: Error: instruction missing MVE vector predication code -- `vidup.u32 q0,r0,#1'
[^:]*:37: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
[^:]*:38: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
[^:]*:40: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `viwdupt.u32 q0,r0,r1,#1'
[^:]*:43: Error: instruction missing MVE vector predication code -- `viwdup.u32 q0,r0,r1,#1'

